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september 2010 doc id 15136 rev 2 1/31 AN2847 application note lis331dlh: 2 g /4 g /8 g digital output high performance ultra low-power 3-axis accelerometer introduction this document provides application information for the low-voltage 3-axis digital output linear mems accelerometer provided in the lga package. the lis331dlh is a high performance ultra low-power 3-axis linear accelerometer, which belongs to the ?nano? family of mems accelerometers, with digital i 2 c/spi serial interface standard output. the device features ultra low-power operational modes that allow advanced power saving and smart sleep to wakeup functions. the lis331dlh has dynamically user-selectable full scales of 2 g /4 g /8 g and is capable of measuring acceleration with output data rates from 0.5 hz to 1 khz. the self-test capability allows th e user to check the functioning of the sensor in the final application. the device can be configured to generate interrupt signals in response to inertial wake- up/free-fall events, or based on the position of the device itself. the thresholds and timing of interrupt generators are programmable by the end user while fully operational. the lis331dlh is available in a small, thin plastic land grid array (lga) package, and is guaranteed to operate over a wide temperature range of -40 c to +85 c. www.st.com
contents AN2847 2/31 doc id 15136 rev 2 contents 1 register table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 start-up sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1 reading acceleration data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1.1 using the status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1.2 using the data-ready signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1.3 using the block data update feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2 output data rate selection and reading timing . . . . . . . . . . . . . . . . . . . . . . 9 2.3 data ready vs. interrupt signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.4 understanding acceleration data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.4.1 data alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.4.2 big-little endian selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.4.3 example of acceleration data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3 operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.1 normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.2 power down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.3 low power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.4 sleep to wake . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.4.1 entering the sleep to wake mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.4.2 exiting the sleep to wake mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4 high pass filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.1 filter configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.1.1 normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.1.2 reference mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5 interrupt generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.1 duration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.2 threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.3 free-fall and wake-up interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.4 inertial wake-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.4.1 hp filter bypassed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
AN2847 contents doc id 15136 rev 2 3/31 5.4.2 using the hp filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.5 free-fall detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.6 6d direction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 6 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
list of tables AN2847 4/31 doc id 15136 rev 2 list of tables table 1. register table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 table 2. output data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 3. timing value to prevent data loss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 4. data signal on int 1 and int 2 pads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 5. output data register content vs. acceleration (fs = 2 g) . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 6. power mode and low-power output data rate configurations . . . . . . . . . . . . . . . . . . . . . . . 13 table 7. ctrl_reg1 - data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 8. ctrl_reg5 - sleep to wake configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 9. power consumption - normal mode (a) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 10. power consumption - low power mode (a) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 11. turn on time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 12. high-pass filter mode configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 13. high-pass filter cut-off frequency configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 14. reference mode lsb value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 15. interrupt mode configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 16. duration lsb value in normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 0 table 17. duration lsb value in low power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 18. threshold lsb value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 19. intx_src register in 6d position . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 20. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
AN2847 list of figures doc id 15136 rev 2 5/31 list of figures figure 1. reading timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 2. interrupt and dataready signal generation block diagram. . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 3. data-ready signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 4. sleep to wake mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 5. high pass filter connections block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 6. hp_filter_reset readings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 8 figure 7. reference mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 8. free-fall, wake-up interrupt generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 9. ff_wu_cfg high and low. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 10. inertial wake-up interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 11. free-fall interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 12. zh, zl, yh, yl, xh, xl behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 13. 6d movement vs. 6d position . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 14. 6d recognized positions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
register table AN2847 6/31 doc id 15136 rev 2 1 register table table 1. register table register name address bit7 bi t6 bit5 bit4 bit3 bit2 bit1 bit0 who_am_i 0fh 0 0 1 1 0 0 1 0 ctrl_reg1 20h pm2 pm1 pm0 dr1 dr0 zen yen xen ctrl_reg2 21h boot hpm1 hpm0 fds hpen2 hpen1 hpcf1 hpcf0 ctrl_reg3 22h ihl pp_od lir2 i2_cf1 i2_cf0 lir1 i1_cf1 i1_cf0 ctrl_reg4 23h bdu ble fs1 fs0 stsign 0 st sim ctrl_reg5 24h - - - - - - turnon1 turnon0 hp_filter_reset 25h - - - - - - - - reference 26h ref7 ref6 ref5 ref4 ref3 ref2 ref1 ref0 status_reg 27h zyxor zor yor xor zyxda zda yda xda outx_l 28h xd7 xd6 xd5 xd4 xd3 xd2 xd1 xd0 outx_h 29h xd15 xd14 xd13 xd12 xd11 xd10 xd9 xd8 outy_l 2ah yd7 yd6 yd5 yd4 yd3 yd2 yd1 yd0 outy_h 2bh yd15 yd14 yd13 yd12 yd11 yd10 yd9 yd8 outz_l 2ch zd7 zd6 zd5 zd4 zd3 zd2 zd1 zd0 outz_h 2dh zd15 zd14 zd13 zd12 zd11 zd10 zd9 zd8 int1_cfg 30h aoi 6d zhie zlie yhie ylie xhie xlie int1_src 31h - ia zh zl yh yl xh xl int1_ths 32h 0 ths6 ths5 ths4 ths3 ths2 ths1 ths0 int1_duration 33h 0 d6 d5 d4 d3 d2 d1 d0 int2_cfg 34h aoi 6d zhie zlie yhie ylie xhie xlie int2_src 35h - ia zh zl yh yl xh xl int2_ths 36h 0 ths6 ths5 ths4 ths3 ths2 ths1 ths0 int2_duration 37h 0 d6 d5 d4 d3 d2 d1 d0
AN2847 start-up sequence doc id 15136 rev 2 7/31 2 start-up sequence once the device is powered up it automatically downloads the calibration coefficients from the embedded flash memory to the internal registers. when the boot procedure is complete (i.e. after about 5 m illiseconds), the device automati cally enters power-down mode. to turn on the device and gather acceleration data, it is necessary to select one of the operating modes through the ctrl_reg1 register, and to enable at least one of the axes. the following general-purpose sequence can be used to configure the device: 1. write ctrl_reg1 2. write ctrl_reg2 3. write ctrl_reg3 4. write ctrl_reg4 5. write reference 6. write int1_ths 7. write int1_dur 8. write int2_ths 9. write int2_dur 10. read hp_filter_reset (if filter is enabled) 11. write int1_cfg 12. write int2_cfg 13. write ctrl_reg5 register values can be changed at any time, and with the device in any operating mode. modifications take effect immediately. note that in case of changes in full scale, odr or enabling/disabling of self-test, the output of the device will require 1 ms + 1/odr to settle (see table 11 ). if the hp filter cut-off frequency is changed, the filt er can be reset by reading th e hp_filter_reset register.
start-up sequence AN2847 8/31 doc id 15136 rev 2 2.1 reading acceleration data 2.1.1 using the status register the device features a status_reg register which should be polled to check when a new set of data is available. the reading procedure is the following: the check performed at step 3 determines whether the reading rate is adequate compared to the data production rate. in cases where one or more acceleration samples have been overwritten by new data due to an excessively slow reading rate, the zyxor bit of the status_reg register is set to 1. the overrun bits are automatically cleared when all the data present inside the device have been read and new data have not been produced in the meantime. 2.1.2 using the data-ready signal the device may be configured to have one hw signal to determine when a new set of measurement data is available for reading. this signal is represented by the xyzda bit of the status_reg register. the signal can be driven to the int1 or int2 pins and its polarity set to active-low or active-high through the ctrl_reg3 register. the interrupt is reset when the higher part of the data of all the enabled channels has been read. 2.1.3 using the bloc k data update feature if the reading of the acceleration data is particularly slow and cannot be (or does not need to be) synchronized with either the xyzda bit within the status_reg or with the rdy signal, it is strongly recommended to set the bdu (block data update) bit in ctrl_reg4 to 1. this feature prevents the need to read the val ues (most significant and least significant parts of the acceleration data) related to different samples. in particular, when the bdu is activated, the data registers related to each channel always contain the most recent acceleration data produced by the device. but if the reading of a given pair (i.e. outx_h and outx_l, outy_h and outy_l, outz_h and outz_l) is initiated, the refresh for that pair is blocked until both the msb and lsb parts of the data are read. 1 read status_reg 2 if status_reg(3) = 0 then goto 1 3 if status_reg(7) = 1 then some data have been overwritten 4 read outx_l 5 read outx_h 6 read outy_l 7 read outy_h 8 read outz_l 9 read outz_h 10 data processing 11 goto 1
AN2847 start-up sequence doc id 15136 rev 2 9/31 note: bdu only guarantees that outx(y, z)_l and outx(x,z)_h have been sampled at the same moment. if the reading speed is too low, it is possible, for example, to read x and y sampled at t1 and z sampled at t2. 2.2 output data rate se lection and reading timing the output data rate is user selectable through the drx bits of the ctrl_reg1 (20h) register. at power-on-reset, the drx are reset to 0, thus providing a default output data rate of 50 hz. the analog signal coming from the mechanical sensor is filtered by a low pass filter before being converted by the internal adc. the frequency at -3 db of the low pass filter determines the effective system resolution. the cut-off frequency depends on the dr<1:0> bits in the ctrl_reg1 (20h) register ( table 2 ). note: the output data rate precisio n is related to the internal osc illator; an error of +/- 10% should be taken into account. a typical reading period is defined which is 616 s shorter than the output data rate period, in order to prevent the loss of any data produced. during this time period the reading of the data must be performed and the dataready signal can be used as a trigger to begin the reading sequence. at the end of the complete sequence, the dataready signal goes down and the rising edge that follows signals that new data are available. if this minimum reading frequency is not observed, some data loss is possible and the dataready signal is no longer considered a trigger signal. the status register can be used to infer the occurrence of an overrun. figure 1. reading timing table 2. output data rate dr1, dr0 output data rate analog filter cut-off frequency (-3 db) 00 50 hz 37 hz 01 100 hz 74 hz 10 400 hz 292 hz 11 1000 hz 780 hz table 3. timing value to prevent data loss time description typ t0 data rate 1/odr $ata2eady 4 4 4 .ewdataavailable ".w
start-up sequence AN2847 10/31 doc id 15136 rev 2 2.3 data ready vs. interrupt signal the device has two pins which can be activated to generate either the data-ready signal or the interrupt signal. the functionality of the pins is selected acting on bit i1(2)_cfgx bits of the ctrl_reg3 register, according to table 4 and the block diagram shown in figure 2 . figure 2. interrupt and dataready signal generation block diagram in particular, the data-ready (dr) signal rises to 1 when a new set of acceleration data has been generated and is available for reading. the signal is reset after all the enabled channels are read through the serial interface. t1 reading period t0-t2 t2 new data generation 616 s table 3. timing value to prevent data loss time description typ table 4. data signal on int 1 and int 2 pads i1(2)_cfg1 i1(2)_cfg0 int 1(2) pin 0 0 interrupt 1 (2) source 0 1 interrupt 1 source or interrupt 2 source 1 0 data ready 1 1 boot running ".w &ree &all 7ake 5p )nterrupt #ounter /$2#lock ).4x?$52!4)/. ,atch #42,?2%',)2 'enerator to 0ad )! ).4 ?32# ).4 &ree &all 7ake 5p )nterrupt #ounter /$2#lock ).4x?$52!4)/. ,atch #42,?2%',)2 'enerator )! ).4 ?32# $ata2eadysignal $ata2eady 3ignal 'enerator "//4 ) ?#&' ) ?#&'
AN2847 start-up sequence doc id 15136 rev 2 11/31 figure 3. data-ready signal 2.4 understanding acceleration data the measured acceleration data are sent to the outx_h, outx_l, outy_h, outy_l, outz_h and outz_l registers. these registers contain, respectively, the most significant part and the least significant part of the acceleration signals acting on the x, y and z axes. the complete acceleration data for the x (y, z) channel is given by the concatenation outx_h & outx_l (outy_h & outy_l, outz_h & outz_l) and is expressed as a 2?s complement number. 2.4.1 data alignment acceleration data are represented as 16-bit numbers and are left justified. 2.4.2 big-little endian selection the lis331dlh allows the swapping of the content of the lower and the upper part of the acceleration registers (i.e. outx_h with outx_l), to be compliant with both little-endian and big-endian data representations. ?little endian? means that the low-order byte of the number is stored in memory at the lowest address, and the high-order byte at the highest address (the little end comes first). this mode corresponds to bit ble in the ctrl_reg4 reset to 0 -default configuration-. conversely, ?big endian? means that the high-order byte of the number is stored in memory at the lowest address, and the low-order byte at the highest address. 2.4.3 example of acceleration data the following table provides a few basic examples of the data th at will be read in the data registers when the device is subject to a given acceleration. the values listed in the table are based on the assumption that the device is perfectly calibrated (i.e., no offset, no gain error, etc.) and show the effect of the ble bit. ".w 2$9 $!4!2%!$ . e l p m a 3 l e c c ! . e l p m a 3 l e c c ! ! 4 ! $ , % # # ! 89: 89:
start-up sequence AN2847 12/31 doc id 15136 rev 2 table 5. output data register content vs. acceleration (fs = 2 g ) acceleration values ble = 0 ble = 1 register address 28h 29h 28h 29h 0 g 00h 00h 00h 00h 350 mg e0h 15h 15h e0h 1 g 00h 40h 40h 00h -350 mg 20h eah eah 20h -1g 00h c0h c0h 00h
AN2847 operating modes doc id 15136 rev 2 13/31 3 operating modes the lis331dlh can operate in the following four modes, which can be selected through the configuration of ctr_reg1 and ctrl_reg5: normal mode power down low power sleep to wake with reference to the datasheet of the device, the powermode (pm) and datarate (dr) bits of ctrl_reg1 register are used to select the basic operating modes (power down, normal mode and low power). the turnon bits of the ctrl_reg5 register are used to enable sleep to wake, which is an advanced mode involving the interrupt configuration also. note: the pmx bits are disabled if the turnonx bits of the ctrl_reg5 are not configured as zeros. table 6. power mode and low-power output data rate configurations pm2 pm1 pm0 power mode selection output data rate [hz] odr lp 000 power down -- 0 0 1 normal mode odr 0 1 0 low power 0.5 011 low power 1 100 low power 2 101 low power 5 110 low power 10 table 7. ctrl_reg1 - data rate dr! dr0 data rate generation [hz] odr 00 50 01 100 10 400 1 1 1000
operating modes AN2847 14/31 doc id 15136 rev 2 table 9 and table 10 show the typical power consumption values for the different operating modes. note: higher data rates correspond to lower device resolution. 3.1 normal mode in normal mode, data are generated at the data rate (odr) selected through the dr bits and for the axis enabled through the zen, yen and xen bits of the ctrl_reg1 register. data generated for a disabled axis is 00h. data interrupt generation is active and configured through the int1_cfg and int2_cfg registers. 3.2 power down mode when the device is in power down mode, almost all internal blocks of the device are switched off to minimize power consumption. digital interfaces (i 2 c and spi) are still active to allow communication with the device. the content of the configuration register is preserved and output data registers are not updated, thus keeping in memory the last data sampled before going to power down mode. typical turn-on time to return to normal mode is 1 ms + 1/odr. table 8. ctrl_reg5 - sleep to wake configuration turnon1 turnon0 sleep to wake status 0 0 sleep to wake function disabled 01 an interrupt event has occurred and the system is generating data at odr 1 0 not allowed 1 1 sleep to wake function enabled table 9. power consumption - normal mode ( a) odr 50 hz 100 hz 400 hz 1000 hz power consumption 250 255 290 370 table 10. power consumption - low power mode (a) odr\odr lp 0.5 hz 1 hz 2 hz 5 hz 10 hz 50 hz 10 20 30 60 99 100 hz 10 15 20 40 80 400 hz 10 15 20 40 80 1000 hz 5 10 15 30 60
AN2847 operating modes doc id 15136 rev 2 15/31 3.3 low power mode when the device is in low power mode data are produced at the odr lp selected by the pm bits of ctrl_reg1. turn on time follows the same rules as for power down mode ( table 11 ). 3.4 sleep to wake the sleep to wake function, in conjunction with low power mode, allows further reduction of system power consumption and the development of new smart applications. the lis331dlh can be set in a low-power operating mode, characterized by lower date rate refreshments. in this way the device, even if ?sleeping?, continues sensing acceleration and generating interrupt requests. when the sleep to wake function is activated, the lis331dlh is able to automatically wake up as soon as the interrupt event has been detected, increasing the output data rate and bandwidth. with this feature the system can be efficiently switched from low power mode to full performance, depending on user-selectable positioning and acceleration events, thus ensuring power saving and flexibility. the sleep to wake function is activate d through turnonx bits of ctrl_reg5 ( table 8 ). when the device is in sleep to wake mode, it automatically samples the acceleration data at odr lp to verify if interrupt conditions are reached. when an interrupt event occurs, the device goes back to generate data at odr ( figure 4 ). in case interrupt conditions are not reached, the device remains in low power mode at odr lp . the device is ready to immediately generate valid samples as soon as it exits from sleep to wake mode. note: when an interrupt event occurs, the content of ctr_reg5 changes to 0x01 while the content of ctrl_reg1 is left untouched. the pm x bits are ignored. to return to normal mode or low power mode, the turnonx bits of ctrl_reg5 must be set to zero. table 11. turn on time data rate generation (hz) turn on time - typ (ms) 50 21 100 11 400 3.5 1000 2
operating modes AN2847 16/31 doc id 15136 rev 2 figure 4. sleep to wake mode 3.4.1 entering the sleep to wake mode perform the following procedure to set up the sleep to wake function: 1. configure the desired interrupt event (free-fall, wake-up, 6d position or 6d movement). 2. select the desired low power mode (odr lp ) and data rate (o dr) in ctrl_reg1. 3. enable the sleep to wake mode through ctrl_reg5 (turnon1 = turnon0 = 1). once an interrupt event occurs, the turnon bits change to turnon1 = 0 and turnon0 = 1 and the system generates data at odr. the user can re-activate the sleep to wake function by executing step 3 again. 3.4.2 exiting the sleep to wake mode to return to normal mode or to low power mode, the user must disable the sleep to wake function by setting turnon1 = turnon0 = 0. ".w $2 $2 $2 $2 $2 $2 $2 g 7!+%50 4(2%3(/,$ 7ake5p )nterrupt /$2 ,0 $2 $2 $2 /$2
AN2847 high pass filter doc id 15136 rev 2 17/31 4 high pass filter the lis331dlh provides embedde d high-pass filtering capabilit y to easily remove the dc component of the measured acceleration. as shown in figure 5 , it is possible to independently apply the filter on the output data and/or on the interrupts data through the fds, hpen1 and hpen2 bits of the ctrl_reg2 register configuration. this means that it is possible, for example, to obtain filtered data while interrupt generation works on unfiltered data. figure 5. high pass filter connections block diagram 4.1 filter configuration as shown in table 12 , two operating modes are possible for the high-pass filter: : the bandwidth of the high-pass filter depends on the selected odr and on the settings of the hpcfx bits of ctrl_reg2. the high-pass filter cut-off frequencies (f t ) are shown in table 13 . ".w )nterrupt #42,?2%'(0en #42,?2%'&$3 2egs!rray )nterrupt #42,?2%'(0en /utputregs 32#reg 32#reg 3ource 3ource $!4! &),4%2%$$!4! table 12. high-pass filter mode configuration hpm1 hpm0 0 0 normal mode (reset reading hp_reset_filter) 0 1 reference mode 1 0 same as configuration 00h 1 1 not allowed
high pass filter AN2847 18/31 doc id 15136 rev 2 4.1.1 normal mode in this configuration the high-pass filter can be reset by reading the hp_filter_reset register, instantly matching the output data to the input acceleration. figure 6. hp_filter_reset readings 4.1.2 reference mode in reference mode configuration the output data is calculated as the difference between the input acceleration and the content of the reference register. this register is in 2?s complement representation and the value of 1lsb of these 7-bit registers depends on the selected full scale ( table 14 ). table 13. high-pass filter cut-off frequency configuration hpcoeff2,1 f t [hz] data rate = 50 hz f t [hz] data rate = 100 hz f t [hz] data rate = 400 hz f t [hz] data rate = 1000 hz 00 1 2 8 20 01 0.5 1 4 10 10 0.25 0.5 2 5 11 0.125 0.25 1 2.5 ".w )nput!cceleration &iltered$ata table 14. reference mode lsb value full scale reference mode lsb value (mg) 2~16 4~31 8~63
AN2847 high pass filter doc id 15136 rev 2 19/31 figure 7. reference mode ".w )nput!cceleration &iltered$ata 2%&%2%.#%enable 2%&%2%.#%
interrupt generation AN2847 20/31 doc id 15136 rev 2 5 interrupt generation the lis331dlh can provide two interrupt si gnals and offers several possibilities for personalizing these signals. the registers involved in the interrupt generation behavior are ctrl_reg3, int1_cfg, int2_cfg, int1_ths, int2_ths, int1_duration, and int2_duration. the lis331dlh interrupt signal can behave as free-fall, wake-up or 6d orientation detection. whenever an interrupt condition is verified, the interrupt signal is generated and by reading the int1_src and int2_src registers it is possible to detect which condition has occurred. 5.1 duration the content of the duration registers set the minimum duration of the interrupt event to be recognized. duration steps and maximum values depend on the odr chosen. when in normal mode, duration time is measured in n/odr, where n is the content of the duration register and odr is 50, 100, 400, 1000 hz. when in low power mode, duration time is measured in n/odr lp , where n is the content of the duration register and odr lp is 0.5, 1, 2, 5, 10 hz. table 15. interrupt mode configuration aoi 6d interrupt mode 0 0 or combination of interrupt events 0 1 6 direction move ment recognition 1 0 and combination of interrupt events 1 1 6 direction position recognition table 16. duration lsb value in normal mode odr (hz) duration lsb value (ms) 50 20 100 10 400 2.5 1000 1
AN2847 interrupt generation doc id 15136 rev 2 21/31 5.2 threshold threshold registers define the reference accelerations used by the interrupt generation circuitry. the value of 1lsb of these 7-bit registers depends on the selected full scale ( table 18 ). 5.3 free-fall and wake-up interrupts the lis331dlh interrupt signals can behave as free-fall, wake-up or 6d orientation detection. when an interrupt condition is verified, the interrupt signal is generated and by reading the int1_src and int2_src registers it is possible to determine which condition has occurred. the free-fall signal (ff) and wake-up signal (wu) interrupt generation block is represented in figure 8 . ff or wu interrupt generation is selected through the aoi bit in intx_cfg register. if the aoi bit is ?0?, signals coming from comparators are put in logical ?or?. depending on the values written in the int1_cfg register, every time the value of at least one of the enabled axes exceeds the threshold written in module in intx_ths registers, a wu interrupt is generated. otherwise, if the aoi bit is ?1?, signals coming from the comparators go into a ?nand? port. in this case, an interrupt signal is generated only if all the enabled axes exceed the threshold written in the intx_ths register. the lirx bits of the ctrl_reg3 can be used to determine whether or not the interrupt request must be latched. if the lirx bit is ?0? (default value), the interrupt signal goes high when the interrupt condition is satisfied and immediately returns low if the inte rrupt condition is no longer verified. otherwise, if the lirx bit is ?1?, when an interrup t condition is applied, the interrupt signal remains high even if the condition returns to a non-interrupt status, until a reading of the intx_src register is performed. table 17. duration lsb value in low power mode odr (hz) duration lsb value (s) 0.5 2 11 20.5 50.2 10 0.1 table 18. threshold lsb value full scale threshold lsb value (mg) 2~16 4~31 8~63
interrupt generation AN2847 22/31 doc id 15136 rev 2 the zhie, zlie, yhie, ylie, xhie and hlie bits of the intx_cfg register select on which axis the interrupt decision must be performed, and in which direction the threshold must be exceeded to generate the interrupt request. figure 8. free-fall, wake-up interrupt generator the threshold module which is used by the system to detect free-fall or inertial wake-up events is defined by the intx_ths registers. the threshold value is expressed over 7 bits as an unsigned number and is symmetrical around the zero-g level. xh (yh, zh) is true when the unsigned acceleration value of the x (y, z) channel is higher than intx_ths. similarly, xl, (yl, zl) low is true when the unsigned acceleration value of the x (y, z) channel is lower than intx_ths. refer to figure 9 for additional details. ths reg |b|>a? |b|a? |b|a? |b| AN2847 interrupt generation doc id 15136 rev 2 23/31 figure 9. ff_wu_cfg high and low !-v &ull3cale &ull3cale glevel 4hresholdmodule 4hresholdmodule 89: high 89: high 89 : low 0ositive .egative acceleration acceleration
interrupt generation AN2847 24/31 doc id 15136 rev 2 5.4 inertial wake-up the wake-up interrupt refers to a specific configuration of the intx_ctrl registers that allow the interrupt generation when the acceleration on the configured axis exceeds a defined threshold ( figure 10 ). figure 10. inertial wake-up interrupt 5.4.1 hp filter bypassed this paragraph provides a basic algorithm which shows the practical use of the inertial wake-up feature. in particular, with the code below, the device is configured to recognize when the absolute acceleration along either x or y axis exceeds a preset threshold (250 mg used in the example). the event which triggers the interrupt is latched inside the device and its occurrence is signaled through the usage of the int1 pin. 0 g wake up threshold wkp interrupt 0 g wake up threshold wkp interrupt wu interrupt 1 write 2fh into ctrl_reg1 // turn on the sensor and enable x, y and z // odr = 100 hz 2 write 00h into ctrl_reg2 // high pass filter disabled 3 write 00h into ctrl_reg3 // latched interrupt active high on int1 pad 4 write 00h into ctrl_reg4 // fs = 2 g 5 write 00h into ctrl_reg5 // sleep to wake disabled 6 write10h into int1_ths // threshold = 250 mg 7 write 00h into int1_duration // duration = 0 8 write 0ah into int1_cfg // enable xh and yh interrupt generation 9 poll int1 pad; if int1=0 then goto 8 // poll rdy/int pin waiting for the // wake-up event 10 read int1_src // return the event that has triggered the // interrupt 11 (wake-up event has occurred; insert your code here) // event handling 12 goto 8
AN2847 interrupt generation doc id 15136 rev 2 25/31 5.4.2 using the hp filter the code which follows provides a basic routine showing the practical use of the inertial wake-up feature performed on high-pass filtered data. in particular, the device is configured to recognize when the high-frequency component of the acceleration applied along either the x, y or z axis exceeds a preset threshold (250 mg is used in the example). the event which triggers the interrupt is latched inside the device and its occurrence is signalled through the int1 pin. at step 8, a dummy read at the hp_filte r_reset register is performed to set the current/reference acceleration/tilt state against which the device performed the threshold comparison. this read may be performed any time it is required to set the orientation/tilt of the device as a reference state without waiting for the filter to settle. 5.5 free-fall detection free-fall detection refers to a specific configuration of the intx_ctrl registers that allows the recognition of device free-fall: the acceleration measurements along all the axes go to zero. in real cases, a ?free-fall zone? is defined around the zero- g level, where all accelerations are small enough to generate the interrupt ( figure 11 ). 1 write 2fh into ctrl_reg1 // turn on the sensor, enable x, y and z // odr = 100 hz 2 write 15h into ctrl_reg2 // high pass filter enabled on data and interrupt1 3 write 00h into ctrl_reg3 // latched interrupt active high on int1 pad 4 write 00h into ctrl_reg4 // fs = 2 g 5 write 00h into ctrl_reg5 // sleep to wake disabled 6 write10h into int1_ths // threshold = 250 mg 7 write 00h into int1_duration // duration = 0 8 read hp_filter_reset // dummy read to force the hp filter to // actual acceleration value // (i.e. set reference acceleration/tilt value) 9 write 2ah into int1_cfg // configure desired wake-up event 10 poll int1 pad; if int1 = 0 then goto 9 // poll int1 pin waiting for the // wake-up event 11 (wake-up event has occurred; insert your code here) // event handling 12 read int1_src // return the event that has triggered the // interrupt and clear interrupt 13 (insert your code here) // event handling 14 goto 9
interrupt generation AN2847 26/31 doc id 15136 rev 2 figure 11. free-fall interrupt this paragraph provides the fundamentals for using the free-fall detection feature. in particular, the software routine which configures the device to detect and signal free-fall events is as follows: the code sample exploits a threshold set at 350 mg for free-fall recognition and the event is notified by the hardware signa l int1. at step 5, the int1_dura tion register is configured to ignore events that are shorter than 3/dr = 3/100 ~= 30 ms in order to avoid false detections. once the free-fall event has occurred, a read at the int1_src register clears the request and the device is ready to recognize other events. 5.6 6d direction the lis331dlh features an adva nced capability to detect the or ientation of the device in space. the 6d direction function can be enabled through the aoi and 6d bits of the int1_cfg register ( table 3 ). when configured for the 6d function, the zh, zl, yh, yl, xh, 1 write 2fh into ctrl_reg1 // turn on the sensor, enable x, y and z // odr = 100 hz 2 write 00h into ctrl_reg2 // high pass filter disabled 3 write 04h into ctrl_reg3 // latched interrupt on int1 4 write 16h into int1_ths // set free-fall threshold = 350mg 5 write 03h into int1_duration // set minimum event duration 6 write 95h into int1_cfg // configure free-fall recognition 7 poll int1 pad; if int1 = 0 then goto 8 // poll int1 pin waiting for the free-fall event 8 (free-fall event has occurred; insert your code here) // event handling 9 read int1_src register // clear interrupt request 10 goto 7 !-v g &2%%&!,, :/.% 8 9 : &&)nterrupt
AN2847 interrupt generation doc id 15136 rev 2 27/31 xl bits of intx_src send information about the value of the acceleration generating the interrupt when it exceeds the threshold, and whether the acceleration value is positive or negative. more specifically: zh (yh, xh) is 1 when the sensed acceleration is greater than the threshold in the positive direction. zl, (yl, xl) is 1 when the sensed acceleration is greater than the threshold in the negative direction. figure 12. zh, zl, yh, yl, xh, xl behavior there are two possible configurations for the 6d direction function: 6d movement recognition : in this configuration the interrupt is generated when the device moves from one direction (known or unknown) to a different, known direction. the interrupt is active only for 1/odr. 6d position recognition : in this configuration the interrupt is generated when the device is stable in a known direction. the in terrupt is active as long as the position is maintained, as shown in figure 13 , (a) and (b). in figure 13 , the 6d movement line shows the behavior of the interrupt when the device is configured for 6d movement recognition on the x and y axes (int1_cfg = 0x4ah), while the 6d position line shows the behavior of the interrupt when the device is configured for 6d position recognition on the x and y axes (int1_cfg = 0xcah). int1_ths is set to 0x21. with reference to figure 14 , the device has been configured for the 6d position function on the x, y and z axes. table 19 shows the content of the int1_src register for each position. !-v &ull3cale &ull3cale glevel 4hresholdmodule 4hresholdmodule 8(9(:( 8,9,:, 0ositive .egative acceleration acceleration 8(9(:( 8,9,:,
interrupt generation AN2847 28/31 doc id 15136 rev 2 figure 13. 6d movement vs. 6d position figure 14. 6d recognized positions !-v 8 9 : $0osition $-ovement a b !-v 8 9 : "ottom 8 9 : 8 9 : 8 9 : 8 9 : 8 9 : 8 9 : 8 9 : 8 9 : 9 8 : 8 9 : 4op 8 9 : 4op b a d c f e
AN2847 interrupt generation doc id 15136 rev 2 29/31 table 19. intx_src register in 6d position case ia zh zl yh yl xh xl (a)1000100 (b)1000010 (c)1000001 (d)1001000 (e)1100000 (f)1010000
revision history AN2847 30/31 doc id 15136 rev 2 6 revision history table 20. document revision history date revision changes 26-jan-2009 1 initial release. 08-sep-2010 2 updated table 5: output data register content vs. acceleration (fs = 2 g) .
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